library verilog;
use verilog.vl_types.all;
entity ODDRXB is
    generic(
        REGSET          : string  := "RESET"
    );
    port(
        DA              : in     vl_logic;
        DB              : in     vl_logic;
        LSR             : in     vl_logic;
        CLK             : in     vl_logic;
        Q               : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of REGSET : constant is 1;
end ODDRXB;
